With continuous scaling down of transistors, HKMG (High K dielectric layer and Metal Gate) technology has become essential for manufacture processes of 45 nm and beyond. In the HKMG technology, the Gate Last approach is widely favored by numerous leading semiconductor companies. Among them, some companies (for example, Intel from the U.S.) have already produced HKMG-based products according to the gate-last process. The so-called gate-last process means that in a process of manufacturing a transistor, a dummy gate is firstly formed, and then processes, such as forming a spacer by deposition and etching and forming source/drain regions by source/drain implantations, are performed to form components of the transistor other than a gate, and finally the dummy gate is replaced with the gate for the transistor. Generally, the dummy gate comprises an amorphous silicon or polysilicon dummy gate formed on a silicon dioxide layer, and the finally-formed transistor gate comprises a metal gate in the HKMG technology.
So far the gate last process presents some unique advantages. For example, negative impacts resulted from a high temperature process can be mitigated. In particular, restrictions on selection of the metal gate material due to high temperature can be removed. Further, the gate-last process facilitates improving significant stress in the transistor channel, which is particularly useful for improving performances of PFETs. However, there are still some difficulties in the existing gate-last process, for example, formation of ultra-fine lines (45 nm or below), precise control of critical dimensions and profile of a gate, and control of profile and remaining thickness of a hard mask structure, or the like. Therefore, there is a need for a new gate last process, in particular, a process for forming a dummy gate, to address the above difficulties, thereby mitigating problems in manufacturing a transistor and guaranteeing performances of the transistor.